The present invention relates, in general, to the field of systems and methods for high speed integrated circuit (xe2x80x9cICxe2x80x9d) testing. More particularly, the present invention relates to a low cost system and method for wafer probe testing of semiconductor IC devices at a high on-chip rated speed while input and output signals to the device may be operated at a relatively slower rate.
Current techniques for testing ICs are implemented using various techniques such as output data compression, the simultaneous probing of multiple die, on-chip state machines to allow functional testing of circuit subcircuits through built in self test (xe2x80x9cBISTxe2x80x9d) and the like. However, none of the known methods provide a means for device testing at multiples of the input test signal rates. In this regard, there is currently no known technique for testing an integrated circuit device at its maximum operating frequency with a probe stimulus lower than the operating frequency of the device itself.
High speed integrated circuit memory devices can be particularly difficult to test. Often, clock rates or input/output (xe2x80x9cI/Oxe2x80x9d) signal rates for high speed memories exceed the capabilities of production and engineering automatic test equipment. State-of-the-art test equipment performance is usually dictated by near-term performance of high volume commodity memories.
Special high speed memory products targeted for graphics applications and other specialty high speed markets often push production testers beyond their limits. The emergence of very high speed embedded memories that interface to other on-chip circuitry to operate at speeds of from two to four times faster than commodity high volume memories using the same process and layout technologies has resulted in an even greater disparity between memory speed and tester capability. Even synchronous dynamic random access memory (xe2x80x9cSDRAMxe2x80x9d) and double data rate (xe2x80x9cDDRxe2x80x9d) SDRAMs are designed for operation at constantly faster clock frequencies thereby requiring fast, high cost testers to test these commodity DRAM devices. Further, it is almost always the case that the frequency at which these devices can be tested using wafer probes is considerably lower than that at which the device must be guaranteed to operate.
The present invention advantageously provides a system and method for low cost testing of integrated circuit devices at their rated speed during wafer probe testing. This enables the device to be operated at its rated speed while input signals to, and output signals from, the device may be operated at a lower speed. Through the technique disclosed herein, a method is provided that enables integrated circuit devices (e.g. memory devices) to be tested at an operational speed faster than that of the test environment itself. This then allows relatively lower cost, lower speed test equipment to be used to test high speed devices and enables devices to be operated at their maximum rated frequency during wafer probe testing.
In an exemplary embodiment of the present invention disclosed herein, a wafer probe signal is used to enable a test function of the device. The test function uses multiple input signals (e.g. pad input signals) to generate on-chip clock signals that are multiples of the input signal rates. Additionally, multiple input signals (e.g. pad input signals) are used to capture data input and accelerate the data rate to the specified data rate of the device where the frequency of the data in on the chip operates at multiples of the data in frequency. In an alternative embodiment, a method is provided that selectively writes either even or odd data internally, while the write timing for the on-chip write is executed at the specified cycle time. Output data may also be selectively outputted (even/odd) at a rate slower than that occurring on the device itself where the output data rate is sufficiently reduced such that an automatic tester can receive and test the output data.
As disclosed herein, the system and method of the present invention may be implemented by means of added on-chip circuitry that interfaces between a memory device and the external test environment. Specifically, the added circuitry can include some or all of the following: a) a method for enabling/disabling the test mode through the use of a program register, special control signal entry or, preferably, the use of a probe pad; b) a clock rate multiplier (e.g. a clock doubler); c) a data-in rate multiplier; d) a data-in selector for reduced write rate; e) broadside state writing (e.g. especially applicable with wide I/O devices; f) a data-out selector for data rate reduction to the device input/output (xe2x80x9cI/Oxe2x80x9d) pads; and g) data-out compression at a 2xc3x97 rate with output rate reduction to a 1xc3x97 rate (e.g. an input-external-clock rate).
In the exemplary embodiment disclosed, a probe pad is used to enable a special test mode. When enabled, the on-chip clock generator enables a clock frequency doubler. The frequency doubler generates a 2xc3x97 frequency clock from the 1xc3x97 frequency external clock signals (two 1xc3x97 clock phases with a 90 degree phase shift between the two clocks). The first phase of the clock uses the CLK input of the device and the second phase uses the device""s CKE input. When in a test mode, the clock suspends any other functions requiring CKE and the CKE input becomes the second phase clock input.
The data-out function operates at a 1xc3x97 rate and on-chip circuitry selectively outputs data on an every-other basis of the 2xc3x97 rate internal clock which results in a 1xc3x97 data out rate. xe2x80x9cEvenxe2x80x9d or xe2x80x9coddxe2x80x9d data groupings are selected by either an additional probe pad or by multiplexing the test mode input selection (even/odd) on an external input pad such as xe2x80x9cchip selectxe2x80x9d (xe2x80x9cCSxe2x80x9d) or a similar method may be employed as indicated with respect to the device CKE input as described above.
Either of two different methods may be employed in implementation of a data-in function:
1) A 2xc3x97 Data Methodxe2x80x94A data accelerating method using two different data inputs and a data multiplexer switched by the 2xc3x97 clock generates the 2xc3x97 internal data. The output of the 2xc3x97 data accelerator is used for two or more input data buses.
2) A 1xc3x97 Data Methodxe2x80x94A method similar to the data-out rate reduction is used for data-in wherein all of the internal data buses run at full speed (e.g. 2xc3x97 frequency) but data is written to every other address location based on the even/odd input/output selector control signal.